{"id":1018,"date":"2026-01-09T12:58:59","date_gmt":"2026-01-09T20:58:59","guid":{"rendered":"https:\/\/blog.lmcache.ai\/?p=1018"},"modified":"2026-03-30T11:52:36","modified_gmt":"2026-03-30T18:52:36","slug":"amd-x-lmcache-amd-gpu-acceleration-with-lmcache","status":"publish","type":"post","link":"https:\/\/identia.digital\/lmcache\/en\/2026\/01\/09\/amd-x-lmcache-amd-gpu-acceleration-with-lmcache\/","title":{"rendered":"AMD \u00d7 LMcache: AMD GPU Acceleration with LMcache"},"content":{"rendered":"\n

<\/p>\n\n\n\n

Introduction<\/h2>\n\n\n\n

LLM inference becomes increasingly challenging as context length grows and workloads scale. Traditional serving engines rely on prefix-based KV cache reuse, which limits opportunities for optimization, especially when processing long, repeated, or overlapping text across different requests.<\/p>\n\n\n\n

LMCache addresses this challenge. It is an extension to LLM serving engines that dramatically reduces time-to-first-token (TTFT) and increases throughput, particularly in long-context scenarios. Unlike traditional prefix-based reuse, LMCache enables fine-grained KV cache reuse for any repeated text, regardless of its position or the serving instance handling the request. By storing reusable KV caches across GPU memory, CPU, DRAM, and local disks, LMCache eliminates redundant computation and preserves valuable GPU cycles.<\/p>\n\n\n\n

When integrated with vLLM, LMCache delivers 3-10x improvements on AMD Instinct\u2122 MI300X GPUs for a wide range of community models, including Qwen3, Llama3, and Qwen-VL.<\/p>\n\n\n\n

By combining LMCache with vLLM, developers achieve significant performance improvement and GPU cycle reduction in many LLM use cases, including long document QA and multi-round QA.<\/p>\n\n\n\n

Long document benchmark<\/h2>\n\n\n\n

To verify, we selected the long document benchmark to compare the performance boost between enabling and disabling LMcache on AMD Instinct\u2122 MI300X GPU by setting the Number of documents as 100, and the document length as 10000 to run the test.<\/p>\n\n\n\n

The following results are generated by using the popular community models including Qwen3\/Llama3\/Qwen-VL, to demonstrate performance boost for different model architectures.<\/p>\n\n\n\n

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This benchmark evaluates the performance of the Llama3 (70B), Qwen2.5 Vison Language models, and Qwen3 series models (specifically the 8B and 30B parameter versions) on a long-document question-answering task, with a key focus on the impact of enabling LMcache (LM Cache).<\/p>\n\n\n\n

The tests were conducted on an Instinct MI300X server. The core methodology involved serving the model using the vLLM framework and running a client-side benchmark script (long_doc_qa.py) that processes many documents, each with a substantial length of 10,000 tokens, while generating 300-token outputs. The primary variable was the number of documents processed, with tests run for 100, 200, and 500 documents.<\/p>\n\n\n\n

The server configuration clearly differentiated between two scenarios: one with LMcache enabled and one without.<\/p>\n\n\n\n

Enabling LMcache involved specific environment variables like PYTHONHASHSEED=0and LMCACHE_MAX_LOCAL_CPU_SIZE, which was tuned for different model sizes (e.g., 200 for Qwen3-8B, 180 and 150 for Qwen3-30B). The vLLM command included the –kv-transfer-configparameter set to use the LMCacheConnector V1. The results presented in the accompanying charts demonstrate a significant performance improvement when LMcache is activated.<\/p>\n\n\n\n

The conclusion that can be drawn is that LMcache effectively optimizes the inference process for long-context scenarios. By caching key-value pairs from the transformer model’s attention mechanism, LMcache reduces redundant computation when processing long, similar documents. This leads to lower latency, particularly for the first token, and higher overall throughput, making the Qwen3 models more efficient and responsive for handling extensive textual data on the MI300X hardware. The tuning of the LMCACHE_MAX_LOCAL_CPU_SIZE parameter for different model sizes also highlights the importance of cache configuration for optimal resource utilization.<\/p>\n\n\n\n

How to reproduce:<\/h3>\n\n\n\n

Server:<\/strong><\/p>\n\n\n\n

Enable LMcache:<\/p>\n\n\n\n

PYTHONHASHSEED=0 \\ \nLMCACHE_MAX_LOCAL_CPU_SIZE=200  \\ \nvllm serve Qwen\/Qwen3-8B \\ \n--tensor-parallel-size 1 \\ \n--kv-transfer-config \\ \n'{\"kv_connector\": \"LMCacheConnectorV1\", \"kv_role\": \"kv_both\"}' \\ \n--gpu-memory-utilization 0.9 \\ \n--load-format dummy \\ \n--trust-remote-code  \n<\/pre>\n\n\n\n
Disable LMcache:<\/p>\n\n\n\n
PYTHONHASHSEED=0  \nvllm serve Qwen\/Qwen3-8B \\ \n--tensor-parallel-size 1 \\ \n--gpu-memory-utilization 0.9 \\ \n--load-format dummy \\ \n--trust-remote-code  \n<\/pre>\n\n\n\n
Client:<\/strong><\/p>\n\n\n\n
Number of documents: 100<\/p>\n\n\n\n
python3 benchmarks\/long_doc_qa\/long_doc_qa.py \\ \n--model Qwen\/Qwen3-8B  \\ \n--num-documents 100 \\ \n--document-length 10000 \\ \n--output-len 300 \\ \n--repeat-count 1 \\ \n--repeat-mode tile \\ \n--max-inflight-requests 4 \n<\/pre>\n\n\n\n
Multi-round QA benchmark<\/strong><\/p>\n\n\n\n
\"Illustration\"\/<\/figure>\n\n\n\n
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Multi-round QA workflow<\/p>\n\n\n\n
To verify, we selected the Multi-round QA benchmark to compare the performance boost between enabling and disabling LMcache on MI300X GPU by setting the Number of users as 20 and number of rounds as 6 to run the test.<\/p>\n\n\n\n
The workload simulated in these benchmarks is a multi-round QA (question answering) task with multiple users interacting with an LLM engine concurrently.<\/p>\n\n\n\n
The following results are generated by using the popular community models including Qwen3\/Llama3\/Qwen-VL, to demonstrate performance boost for different model architectures.<\/p>\n\n\n\n
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How to reproduce:<\/h3>\n\n\n\n
Server:<\/p>\n\n\n\n
Enable LMcache:<\/p>\n\n\n\n
PYTHONHASHSEED=0 \\ \nMIOPEN_USER_DB_PATH=\/app\/miopen \\ \nMIOPEN_FIND_MODE=FAST \\ \nVLLM_USE_V1=1 \\ \nVLLM_ROCM_USE_AITER=1 \\ \nSAFETENSORS_FAST_GPU=1 \\ \nvllm serve Qwen\/Qwen2.5-VL-72B-Instruct \\ \n--tensor_parallel_size=8 \\ \n--trust_remote_code \\ \n--mm-encoder-tp-mode \"data\" \\ \n--load-format dummy \\ \n--gpu-memory-utilization 0.6 \n<\/pre>\n\n\n\n
Disable LMcache**:**<\/p>\n\n\n\n
PYTHONHASHSEED=0 \\ \nMIOPEN_USER_DB_PATH=\/app\/miopen \\ \nMIOPEN_FIND_MODE=FAST \\ \nVLLM_USE_V1=1 \\ \nVLLM_ROCM_USE_AITER=1 \\ \nSAFETENSORS_FAST_GPU=1 \\ \nvllm serve Qwen\/Qwen2.5-VL-72B-Instruct \\ \n--tensor_parallel_size=8 \\ \n--trust_remote_code \\ \n--mm-encoder-tp-mode \"data\" \\ \n--load-format dummy \\ \n--gpu-memory-utilization 0.6 \n<\/pre>\n\n\n\n
Client**:**<\/p>\n\n\n\n
python3 multi-round-qa.py \\ \n    --num-users 20 \\ \n    --num-rounds 6 \\ \n    --qps 1 \\ \n    --shared-system-prompt 1000 \\ \n    --user-history-prompt 2000 \\ \n    --answer-len 100 \\ \n    --model Qwen\/Qwen2.5-VL-72B-Instruct \\ \n    --base-url http:\/\/localhost:8000\/v1 \n<\/pre>\n\n\n\n
Summary<\/h2>\n\n\n\n
The LMCache Long Document QA benchmark is designed to evaluate the performance of large language models when processing and answering questions about lengthy documents. This benchmark demonstrates the AMD Instinct MI300X GPU system’s ability to handle extended context windows and maintain information retrieval accuracy across long documents. for assessing how well LLM serving systems can manage memory-intensive, long-context scenarios.<\/p>\n\n\n\n
The LMBenchmark suite provides a comprehensive evaluation framework for LLM serving systems through multi-round question-answering scenarios. The benchmark simulates realistic concurrent user interactions with three distinct test configurations: ShareGPT (real-world conversations at QPS=1.34), number of users and number of rounds. While enabling systematic comparison of LLM serving systems under varying load conditions, from llama like models to the vison Language models, as well as MoE models, the LMcache provides essential performance improvement for large-scale language model deployments on AMD GPUs.<\/p>\n\n\n\n
LMCache Roadmap<\/h2>\n\n\n\n
In 2026 Q1, the LMCache roadmap is driven by a primary objective to stabilize core features<\/strong> while pioneering advanced global KV cache sharing<\/strong> mechanisms for scalable LLM deployments.<\/p>\n\n\n\n
We are expanding our ecosystem connectivity by integrating with new serving engines such as TRTLLM and Modular, and simultaneously optimizing our storage layer with io_uring and NVMe FDP support for superior I\/O performance. Internally, we are refactoring our RPC infrastructure and memory allocators to enable large-scale peer-to-peer cache sharing and disaggregated pooling.<\/p>\n\n\n\n
More importantly, we are going to strengthen the commitment to adapt heterogeneous hardware, including AMD. We are establishing a dedicated AMD testing platform within our CI\/CD pipeline to ensure seamless compatibility and peak performance on AMD hardware, solidifying LMCache’s role in the next generation of efficient LLM serving infrastructure.<\/p>\n\n\n\n
For more details, please visit our Q1 roadmap at: https:\/\/github.com\/LMCache\/LMCache\/issues\/2350<\/a><\/p>\n\n\n\n
Acknowledgements<\/h2>\n\n\n\n
We would like to thank the many talented people who have contributed to this collaboration:<\/p>\n\n\n\n